PIC MICRO CONTROLLER
• What is PIC?
- A family of Harvard architecture
microcontrollers made by Microchip Technology
- Derived from
the PIC1650 originally developed by General Instrument Microelectronics
Division.
- The name PIC
was originally an acronym for " Peripheral Interface Controller ".
¨ low cost ,wide availability with high
clock speed
¨ availability of low cost or free
development tools
¨ Only 37 instructions to remember
¨ serial programming and re-programming
with flash memory capability
¨ Its code is extremely efficient,
allowing the PIC to run with typically less program memory than its larger
competitors
¨ PIC is very small and easy to
implement for non-complex problems and usually accompanies to the microprocessors
as an interface
n What is New in PIC?:
n High performance RISC CPU with 35 no. of instruction set only
n Harvard Architecture
n Pipelined Instructions
n And a large number of Peripherals In-built
Two Different
Architectures:
We’re used to the Von-Neuman Architecture
v Used in: 80X86 (PCs), 8051, 68HC11, etc.)
v Only one bus between CPU and memory
v RAM and program memory share the same bus and the
same memory, and so must have the same bit width
v Bottleneck: Getting instructions interferes with
accessing RAM
PICs use the Harvard Architecture
Used mostly in RISC CPUs (we’ll get there)
Used mostly in RISC CPUs (we’ll get there)
v Separate program bus and data bus: can be different
widths!
v For example, PICs use:
q Data memory (RAM): a small number of 8bit registers
q Program memory (ROM): 12bit, 14bit or 16bit wide (in
EPROM, FLASH, or ROM)
CISC:
Traditionally,
CPUs are “CISC”
v Complex
Instruction Set Computer (CISC)
v Used
in: 80X86, 8051, 68HC11, etc.
v Many
instructions (usually > 100)
v Many,
many addressing modes
v Usually
takes more than 1 internal clock cycle
(T cycle) to execute
RISC:
PICs and most
Harvard chips are “RISC”
v Reduced
Instruction Set Computer (RISC)
v Used
in: SPARC, ALPHA, Atmel AVR, etc.
v Few
instructions (usually < 50)
v Only
a few addressing modes
v Executes
1 instruction in 1 internal clock cycle (Tcyc) .
Family Core Architecture Differences
n The PIC Family: Cores
¨12bit cores with 33 instructions: 12C50x, 16C5x
¨14bit cores with 35 instructions: 12C67x,16Cxxx
¨16bit cores with 58 instructions: 17C4x,17C7xx
¨‘Enhanced’ 16bit cores with 77 instructions: 18Cxxx
The PIC Family: Speed
•
Can use crystals, clock oscillators, or even an RC
circuit.
•
Some PICs have a built in 4MHz RC clock, Not very
accurate, but requires no external components!
•
Instruction speed = 1/4 clock speed (Tcyc = 4 *
Tclk)
•
All PICs can
be run from DC to their maximum specified speed:
|
4MHz
|
12C50x
|
|
10MHz
|
12C67x
|
|
20MHz
|
16Cxxx
|
PinDiagram
Internal
Architecture:
Features:
v8kB of flash program memory
v368bytes of Data memory
v256-EEPROM data memory
v15 Interrupts
vIn-circuit programming
v3 internal hardware timers
vCapture/Compare/PWM modules
vUp to 8 channels of 10-Bit A/D
vBuilt-in USART for serial communication
v5 digital I/O ports (Up to 22 lines)
vI/O
Ports:
vPIC 16F877A has FIVE I/O Ports
vA total of 33 pins are used for I/O operations.
PORT A
vPort A is 6 bit wide and bi-directional.
vIts corresponding data direction register is TRISA.
vIf TRISA port pin is set to 1,corresponding port A pin will act as an
input pin and vice versa.
vPort A is used for analog inputs.
Port B
vPort B is 8 bit wide and bi-directional.
vIts corresponding data direction register is TRISB.
vIf TRISB port pin is set to 1,corresponding port B pin will act as an
input pin and vice versa.
vPort B is used for Data Transmission.
Port C
vPort C is 8 bit wide and bi-directional.
vIts corresponding data direction register is TRISC.
vIf TRISC port pin is set to 1,corresponding port C pin will act as an
input pin and vice versa.
vPort C is used for control registers(serial communication, I2C
functions,serial data transfer).
Port D
vPort D is 8 bit wide and bi-directional.
v Its corresponding data direction register is TRISD.
vIf TRISD port pin is set to 1,corresponding port D pin will act as an
input pin and vice versa.
vPort D is used as Data port
Port
E
vPort E is 3 bit wide . They are for read, write and chip select
operation.
vEach pin is individually configurable as inputs and outputs.
vPort E is generally used for controlling purposes.
Machine Cycle:
4 cycles per4 cycles per instruction on the
PIC16F87x micro controllers. instruction on the PIC16F87x micro controllers.
Calculations:
v A Machine cycle is the time taken for a data
transfer from or to memory/ I/O Ports.
v Machine cycle is calculated using the formula:
Clock Frequency=6.144MHz
Machine cycle frequency=
6.144 MHz /4
Hence 1 Machine cycle(Time
taken for a data transfer)= 1/T
= 4/
6.144 MHz
= 0.651
µs
Instruction
Cycle:
v An instruction cycle is the time taken to complete
an instruction.
v All instructions in 16F877A are single cycle
instructions except for Branching instruction. They take two machine cycles to
complete an instruction.
PIC On Chip Peripheral overview:
Different PICs have different on-board peripherals some
common peripherals are:
v 3 Timers (0 & 2- 8bits, 1-16 bits)
v 2 Compare/Capture/PWM Modules
v Analog to Digital Converters (ADC) (8, 10 and 12bit,
50ksps)
v Serial communications: UART (RS-232C), SPI, I2C,
CAN
v Pulse Width Modulation (PWM) (10bit)
v Voltage Comparators
v Voltage Reference Modules
v MSSP – Master Synchronous Serial Port
v I2C (Master and Slave)
v SPI (Master and Slave)
v Watchdog timers, Brown out detectors.
Timer modules in PIC 16F877
PIC16F877A has 3 Timers
v Timer 0 - 8 bit
can be used as a Timer/counter
v Timer 1 – 16 bit
can be used as a
Timer/counter
v Timer 2 – 8 bit Timer
can be used as the PWM
time-base for the PWM mode of the CCP
module.
TIMER-0 module
The main
timing/counting features of Timer-0 module are given below.
- Timer-0 module has built in 8 bit timer/counter
- It can be easily readable/writable
- Built in 8 bit software programmable pre-scalar
functions
- Easily select internal/external clock pulses
- Interrupt with overflow from the value FFh to
00h
- Edge selection for external clock pulse
The block
diagram of timer-0 module is given in the figure below. The timer mode is
normally selected by clearing the T0CS bit in the register. In Timer
mode, when the Timer 0 Module increases with every instruction cycle, the TMR0
register is written, the increment is inhibited for the following two
instruction cycles. The user can work around this by writing an adjusted value
to the TMR0 register. Counter mode is selected by setting bit T0CS in Counter
mode. Timer 0 will increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by the Timer 0 Source Edge
Select bit, T0SE. Clearing bit T0SE selects the rising edge. The pre-scaler is
mutually exclusively shared between the Timer0 module and the Watchdog Timer.
Timer-0 Block Diagram
Timer-0 Interrupt
TMR0
interrupt is activated only when the TMR0 register overflows from the value FFh
to 00h. This overflow sets bit TMR0IF .The interrupt can be masked by clearing
bit TMR0IE. Bit TMR0IF must be cleared in software by the Timer 0 module
Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the Processor from Sleep since the timer is shut-off during
Sleep. The main registers associated with timer 0 module is shown in the below
table.
Register
Memory Organization in Timer 0
TIMER 1 MODULE
Timer 1
module is a 16 bit timer/counter unit. That is, it consists of two 8 bit (8+8)
registers (TMR1H, TMR1L) which read and write easily. TMR1 register is a pair
of TMR1H and TMR1L and also its value increment its value from 0000h to FFFFh
and rolls over to 0000h.
Timer 1
module basically operates in two different modes. They are
1)
Timer mode
2)
Counter mode
The
operating mode of timer 1 module is selected by using the clock select bit
(TMR1CS), in timer mode. The timer 1 increases on every instruction cycle. But
in counter mode, it increases on every rising edge of the external clock input.
Timer 1 pin can be enabled/disabled easily by setting/clearing the control bit
(TMR1ON). This timer1 pin also has an internal reset input function. It can be
generated by either of the two CCP modules.
The block
diagram of timer1 module I given in the image below.
Timer-1 Block
Diagram
Timer 1 Operation in Timer
Mode
The Timer
mode can be easily selected by clearing the TMR1CS bit. In this mode, the input
clock to the timer is FOSC/4. The synchronize control bit, T1SYNC, has no
effect since the internal clock is always in sync. Timer1 Operation in
Synchronized
Counter Mode
The
synchronized Counter mode is selected by setting timer 1 synchronized counter
select bit (TMR1CS). In this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin
RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.
Timer1 Counter Operation
Timer 1
generally operates in two modes. Timer 1 may operate in either a Synchronous,
or an Asynchronous mode, depending on the setting of the timer 1 synchronized
counter select (TMR1CS) bit. When Timer1 is being incremented with an external
source, increments occur on a rising edge. After Timer1 is enabled in Counter mode,
the module must first have a falling edge before the counter begins to
increment. Timer1 Operation in Synchronized
Counter Mode
Counter
mode is selected by setting bit TMR1CS. In this mode, the timer increments on
every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set,
or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. If T1SYNC is cleared,
then the external clock input is synchronized with internal phase clocks. The
synchronization is done after the prescaler stage. The prescaler stage is an
asynchronous ripple counter.
In this
configuration, during Sleep mode, Timer1 will not increment even if the
external clock is present since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
Timer1 Operation in
Asynchronous Counter Mode
If control
bit T1SYNC (T1CON<2>) is set, the external clock input is not
synchronized. The timer continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during Sleep and can generate an
interrupt-on-overflow which will wake-up the processor. However, special
precautions in software are needed to read/write the timer. In Asynchronous
Counter mode, Timer 1 cannot be used as a time base for capture or compare
operations.
Timer 1 Oscillator
A crystal
oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator, rated up to 200 kHz. It will continue to
run during Sleep. It is primarily intended for use with a 32 kHz crystal. Below
table shows the capacitor selection for the Timer1 oscillator. The Timer1
oscillator is identical to the LP oscillator.
The user
must provide a software time delay to ensure proper oscillator start-up. The
capacitor selection for various frequencies is shown in the table below.
Capacitor Selection for
Timer-1
Register
memory organization for timer 1 timer/counter module is given in the table
below.
Registers Memory
Organization in Timer 1
TIMER 2 Module
Timer 2 is
an 8-bit timer with a prescaler and a postsaler. It can be used as the PWM
(pulse width modulation) time base for the PWM mode of the CCP module(s). The
block diagram of timer 2 module is given in the figure below. 
Timer-2 Block Diagram
The TMR2
register is readable and writable and is cleared on any device Reset. The input
clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control
bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer 2 module has an 8-bit period
register, PR2. The value of Timer 2 increments from 00h until it matches PR2
and then resets to 00h on the next increment cycle. PR2 is a readable and
writable register. The PR2 register is initialized to FFh upon Reset. The match
output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16
scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF
(PIR1<1>)). Timer 2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Register
memory organization of timer 2 module is given in the table below.
Register Memory
Organization in Timer 2
USART Modules in PIC 16F877
The Universal Synchronous
Asynchronous Receiver Transmitter (USART) module is one of the serial I/O
modules for communication interfacing functions with other devices/units. USART
is also known as a Serial Communications Interface or SCI. The USART can be
configured as a full-duplex asynchronous system that can communicate with
peripheral devices, such as CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that can communicate with
peripheral devices, such as Analog-to-Digital (A/D) or Digital-to-Analog (D/A)
integrated circuits, serial EPROM’s, and so on. Usually PIC 16F877 consists of
two USART modules (USART1, USART2). These ports can be configured in the
following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The USART module also has a
multi-processor communication capability using 9-bit address detection.
USART Baud Rate Generator (BRG)
The baud rate generator (BRG)
supports both the Asynchronous and Synchronous modes of the USART modules. It
is a dedicated 8-bit baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous mode, bit BRGH also
controls the baud rate.
Registers associated with baud rate
generator is shown below.
USART Baud Rate Generator (BRG) –
Registers
USART Asynchronous Mode
In asynchronous mode, the USART
uses standard Non-Return to- Zero (NRZ) format (one Start bit, eight or nine
data bits and one Stop bit). The most commonly used data format is 8 bits. An
on-chip, dedicated, 8-bit Baud Rate Generator can be used to derive standard
baud rate frequencies from the oscillator. The USART transmits and receives the
LSB (Least Significant Bit) first. The transmitter and receiver are
functionally independent but use the same data format and baud rate. The baud
rate generator produces a clock, either x16 or x64 of the bit shift rate,
depending on bit “BRGH “. Parity is not supported by the hardware but can be
implemented in software (and stored as the ninth data bit). Asynchronous mode
is stopped during Sleep. Asynchronous mode is selected by clearing bit SYNC.
The USART Asynchronous module
consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
USART Asynchronous Transmitter
USART transmitter (simply called
TX) is commonly used for data transmission process. The data transmission is
possible through various digital formats. The path of the transmission vary
according to the requirements (e.g.: infrared, Bluetooth, etc.). A simple block
diagram of a USART transmitter is shown below. . The heart of the USART
transmitter is the Transmit (Serial) Shift Register (TSR). The shift register
obtains its data from the Read/Write Transmit Buffer, TXREG. The TXREG register
is loaded with data in software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As soon as the Stop bit is
transmitted, the TSR is loaded with new data from the TXREG register (if
available). The simple block diagram of a USART transmitter is given below.
USART Transmitter Block Diagram
The registers associated with USART
asynchronous transmission is shown in the table below.
USART Asynchronous Transmission –
Registers
USART Asynchronous Receiver
The USART asynchronous receiver is
a data reception unit which is used for data reception from other communication
medias such as RF modules, Bluetooth, infrared modules (IR), etc. The simple
block diagram of a USART receiver is shown in the figure below. The data is
received on the RC7/RX/DT pin and drives the data recovery block. The data
recovery block is actually a high-speed shifter, operating at x16 times the
baud rate; whereas the main receive serial shifter operates at the bit rate or
at FOSC. Once Asynchronous mode is selected, reception is enabled by setting
bit CREN .The heart of the receiver is the Receive (Serial) Shift Register
(RSR). After sampling the Stop bit, the received data in the RSR is transferred
to the RCREG register (if it is empty). If the transfer is complete, flag bit,
RCIF (PIR1<5>), is set.
USART Receiver Block Diagram
The registers associated with the
USART receiver is given in the table below.
USART Asynchronous Reception –
Registers
Applications of USART Modules
1)
Used for Bluetooth communications.
2)
Widely used in Infrared (IR) communications.
3)
USART modules used with other RF communication purposes – AM, FM, QPSK, PSK,
FSK, Wi-Fi, and so on.
CAPTURE/COMPARE/PWM (CCP) Modules in PIC 16F877
Capture-Compare-Pulse-Width-Module (CCP) is a
special module designs for modulation and waveform generation applications.
This module basically works on three different modes (capture/compare and PWM
odes). The PIC 16F877 chip contains two CCP ports (CCP1 and CCP2). Each of this
CCP module contains 16 bit registers which works as
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle registers
The CCP1 and CCP2 modules are identical in its operation
except in its special event trigger operation. In each CCP modules, the
capture, compare and PWM modes using different timer resources. The table below
shows the different CCP modes and its timer resources. The detailed
explanations and functions of CCP module is given below.
CCP Timer Source-Interaction
CCP1 Module
Capture/Compare/PWM Register 1 (CCPR1) is a 16 bit
register comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high
byte). The CCP1CON register controls the operation of CCP1. The special event
trigger is generated by a compare match and will reset Timer1.
CCP2 Module
Capture/Compare/PWM Register 2 (CCPR2) is comprised
of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON
register controls the operation of CCP2. The special event trigger is generated
by a compare match and will reset Timer1 and start an A/D conversion (if the
A/D module is enabled).
Capture Mode
capture is made, the interrupt request flag In
Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when
an event occurs on pin RC2/CCP1.
An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits, CCP1M3:CCP1M0
(CCPxCON<3:0>). When a bit, CCP1IF (PIR1<2>), is set. The interrupt
flag must be cleared in software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is overwritten by the new value.
The block diagram of capture mode is shown below.
Capture Mode
Block Diagram
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair value. When a match occurs,
the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of
control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt
flag bit CCP1IF is set. The compare mode block diagram is shown below.
Compare Mode Block
Diagram
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since the CCP1 pin is
multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared
to make the CCP1 pin an output. Figure shows a simplified block diagram of the
CCP module in PWM mode.
PWM Mode Block Diagram
Setup for PWM Operation
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the CCPR1L
register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2 by
writing to T2CON.
5. Configure the CCP1 module for PWM operation.
The table below shows PWM FREQUENCIES and
RESOLUTIONS AT 20 MHz and registers associated with CCP timer1/2 modules.
Register
Organization-1
Register Organization-2
• What is PIC?
- A family of Harvard architecture
microcontrollers made by Microchip Technology
- Derived from
the PIC1650 originally developed by General Instrument Microelectronics
Division.
- The name PIC
was originally an acronym for " Peripheral Interface Controller ".
¨ low cost ,wide availability with high
clock speed
¨ availability of low cost or free
development tools
¨ Only 37 instructions to remember
¨ serial programming and re-programming
with flash memory capability
¨ Its code is extremely efficient,
allowing the PIC to run with typically less program memory than its larger
competitors
¨ PIC is very small and easy to
implement for non-complex problems and usually accompanies to the microprocessors
as an interface
n What is New in PIC?:
n High performance RISC CPU with 35 no. of instruction set only
n Harvard Architecture
n Pipelined Instructions
n And a large number of Peripherals In-built
Two Different
Architectures:
We’re used to the Von-Neuman Architecture
v Used in: 80X86 (PCs), 8051, 68HC11, etc.)
v Only one bus between CPU and memory
v RAM and program memory share the same bus and the
same memory, and so must have the same bit width
v Bottleneck: Getting instructions interferes with
accessing RAM
PICs use the Harvard Architecture
Used mostly in RISC CPUs (we’ll get there)
Used mostly in RISC CPUs (we’ll get there)
v Separate program bus and data bus: can be different
widths!
v For example, PICs use:
q Data memory (RAM): a small number of 8bit registers
q Program memory (ROM): 12bit, 14bit or 16bit wide (in
EPROM, FLASH, or ROM)
CISC:
Traditionally,
CPUs are “CISC”
v Complex
Instruction Set Computer (CISC)
v Used
in: 80X86, 8051, 68HC11, etc.
v Many
instructions (usually > 100)
v Many,
many addressing modes
v Usually
takes more than 1 internal clock cycle
(T cycle) to execute
RISC:
PICs and most
Harvard chips are “RISC”
v Reduced
Instruction Set Computer (RISC)
v Used
in: SPARC, ALPHA, Atmel AVR, etc.
v Few
instructions (usually < 50)
v Only
a few addressing modes
v Executes
1 instruction in 1 internal clock cycle (Tcyc) .
Family Core Architecture Differences
n The PIC Family: Cores
¨12bit cores with 33 instructions: 12C50x, 16C5x
¨14bit cores with 35 instructions: 12C67x,16Cxxx
¨16bit cores with 58 instructions: 17C4x,17C7xx
¨‘Enhanced’ 16bit cores with 77 instructions: 18Cxxx
The PIC Family: Speed
•
Can use crystals, clock oscillators, or even an RC
circuit.
•
Some PICs have a built in 4MHz RC clock, Not very
accurate, but requires no external components!
•
Instruction speed = 1/4 clock speed (Tcyc = 4 *
Tclk)
•
All PICs can
be run from DC to their maximum specified speed:
|
4MHz
|
12C50x
|
|
10MHz
|
12C67x
|
|
20MHz
|
16Cxxx
|
PinDiagram
Internal
Architecture:
Features:
v8kB of flash program memory
v368bytes of Data memory
v256-EEPROM data memory
v15 Interrupts
vIn-circuit programming
v3 internal hardware timers
vCapture/Compare/PWM modules
vUp to 8 channels of 10-Bit A/D
vBuilt-in USART for serial communication
v5 digital I/O ports (Up to 22 lines)
vI/O
Ports:
vPIC 16F877A has FIVE I/O Ports
vA total of 33 pins are used for I/O operations.
PORT A
vPort A is 6 bit wide and bi-directional.
vIts corresponding data direction register is TRISA.
vIf TRISA port pin is set to 1,corresponding port A pin will act as an
input pin and vice versa.
vPort A is used for analog inputs.
Port B
vPort B is 8 bit wide and bi-directional.
vIts corresponding data direction register is TRISB.
vIf TRISB port pin is set to 1,corresponding port B pin will act as an
input pin and vice versa.
vPort B is used for Data Transmission.
Port C
vPort C is 8 bit wide and bi-directional.
vIts corresponding data direction register is TRISC.
vIf TRISC port pin is set to 1,corresponding port C pin will act as an
input pin and vice versa.
vPort C is used for control registers(serial communication, I2C
functions,serial data transfer).
Port D
vPort D is 8 bit wide and bi-directional.
v Its corresponding data direction register is TRISD.
vIf TRISD port pin is set to 1,corresponding port D pin will act as an
input pin and vice versa.
vPort D is used as Data port
Port
E
vPort E is 3 bit wide . They are for read, write and chip select
operation.
vEach pin is individually configurable as inputs and outputs.
vPort E is generally used for controlling purposes.
Machine Cycle:
4 cycles per4 cycles per instruction on the
PIC16F87x micro controllers. instruction on the PIC16F87x micro controllers.
Calculations:
v A Machine cycle is the time taken for a data
transfer from or to memory/ I/O Ports.
v Machine cycle is calculated using the formula:
Clock Frequency=6.144MHz
Machine cycle frequency=
6.144 MHz /4
Hence 1 Machine cycle(Time
taken for a data transfer)= 1/T
= 4/
6.144 MHz
= 0.651
µs
Instruction
Cycle:
v An instruction cycle is the time taken to complete
an instruction.
v All instructions in 16F877A are single cycle
instructions except for Branching instruction. They take two machine cycles to
complete an instruction.
PIC On Chip Peripheral overview:
Different PICs have different on-board peripherals some
common peripherals are:
v 3 Timers (0 & 2- 8bits, 1-16 bits)
v 2 Compare/Capture/PWM Modules
v Analog to Digital Converters (ADC) (8, 10 and 12bit,
50ksps)
v Serial communications: UART (RS-232C), SPI, I2C,
CAN
v Pulse Width Modulation (PWM) (10bit)
v Voltage Comparators
v Voltage Reference Modules
v MSSP – Master Synchronous Serial Port
v I2C (Master and Slave)
v SPI (Master and Slave)
v Watchdog timers, Brown out detectors.
Timer modules in PIC 16F877
PIC16F877A has 3 Timers
v Timer 0 - 8 bit
can be used as a Timer/counter
v Timer 1 – 16 bit
can be used as a
Timer/counter
v Timer 2 – 8 bit Timer
can be used as the PWM
time-base for the PWM mode of the CCP
module.
TIMER-0 module
The main
timing/counting features of Timer-0 module are given below.
- Timer-0 module has built in 8 bit timer/counter
- It can be easily readable/writable
- Built in 8 bit software programmable pre-scalar
functions
- Easily select internal/external clock pulses
- Interrupt with overflow from the value FFh to
00h
- Edge selection for external clock pulse
The block
diagram of timer-0 module is given in the figure below. The timer mode is
normally selected by clearing the T0CS bit in the register. In Timer
mode, when the Timer 0 Module increases with every instruction cycle, the TMR0
register is written, the increment is inhibited for the following two
instruction cycles. The user can work around this by writing an adjusted value
to the TMR0 register. Counter mode is selected by setting bit T0CS in Counter
mode. Timer 0 will increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by the Timer 0 Source Edge
Select bit, T0SE. Clearing bit T0SE selects the rising edge. The pre-scaler is
mutually exclusively shared between the Timer0 module and the Watchdog Timer.
Timer-0 Block Diagram
Timer-0 Interrupt
TMR0
interrupt is activated only when the TMR0 register overflows from the value FFh
to 00h. This overflow sets bit TMR0IF .The interrupt can be masked by clearing
bit TMR0IE. Bit TMR0IF must be cleared in software by the Timer 0 module
Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the Processor from Sleep since the timer is shut-off during
Sleep. The main registers associated with timer 0 module is shown in the below
table.
Register
Memory Organization in Timer 0
TIMER 1 MODULE
Timer 1
module is a 16 bit timer/counter unit. That is, it consists of two 8 bit (8+8)
registers (TMR1H, TMR1L) which read and write easily. TMR1 register is a pair
of TMR1H and TMR1L and also its value increment its value from 0000h to FFFFh
and rolls over to 0000h.
Timer 1
module basically operates in two different modes. They are
1)
Timer mode
2)
Counter mode
The
operating mode of timer 1 module is selected by using the clock select bit
(TMR1CS), in timer mode. The timer 1 increases on every instruction cycle. But
in counter mode, it increases on every rising edge of the external clock input.
Timer 1 pin can be enabled/disabled easily by setting/clearing the control bit
(TMR1ON). This timer1 pin also has an internal reset input function. It can be
generated by either of the two CCP modules.
The block
diagram of timer1 module I given in the image below.
Timer-1 Block
Diagram
Timer 1 Operation in Timer
Mode
The Timer
mode can be easily selected by clearing the TMR1CS bit. In this mode, the input
clock to the timer is FOSC/4. The synchronize control bit, T1SYNC, has no
effect since the internal clock is always in sync. Timer1 Operation in
Synchronized
Counter Mode
The
synchronized Counter mode is selected by setting timer 1 synchronized counter
select bit (TMR1CS). In this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set, or on pin
RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.
Timer1 Counter Operation
Timer 1
generally operates in two modes. Timer 1 may operate in either a Synchronous,
or an Asynchronous mode, depending on the setting of the timer 1 synchronized
counter select (TMR1CS) bit. When Timer1 is being incremented with an external
source, increments occur on a rising edge. After Timer1 is enabled in Counter mode,
the module must first have a falling edge before the counter begins to
increment. Timer1 Operation in Synchronized
Counter Mode
Counter
mode is selected by setting bit TMR1CS. In this mode, the timer increments on
every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set,
or on pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. If T1SYNC is cleared,
then the external clock input is synchronized with internal phase clocks. The
synchronization is done after the prescaler stage. The prescaler stage is an
asynchronous ripple counter.
In this
configuration, during Sleep mode, Timer1 will not increment even if the
external clock is present since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
Timer1 Operation in
Asynchronous Counter Mode
If control
bit T1SYNC (T1CON<2>) is set, the external clock input is not
synchronized. The timer continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during Sleep and can generate an
interrupt-on-overflow which will wake-up the processor. However, special
precautions in software are needed to read/write the timer. In Asynchronous
Counter mode, Timer 1 cannot be used as a time base for capture or compare
operations.
Timer 1 Oscillator
A crystal
oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The
oscillator is a low-power oscillator, rated up to 200 kHz. It will continue to
run during Sleep. It is primarily intended for use with a 32 kHz crystal. Below
table shows the capacitor selection for the Timer1 oscillator. The Timer1
oscillator is identical to the LP oscillator.
The user
must provide a software time delay to ensure proper oscillator start-up. The
capacitor selection for various frequencies is shown in the table below.
Capacitor Selection for
Timer-1
Register
memory organization for timer 1 timer/counter module is given in the table
below.
Registers Memory
Organization in Timer 1
TIMER 2 Module
Timer 2 is
an 8-bit timer with a prescaler and a postsaler. It can be used as the PWM
(pulse width modulation) time base for the PWM mode of the CCP module(s). The
block diagram of timer 2 module is given in the figure below.
Timer-2 Block Diagram
The TMR2
register is readable and writable and is cleared on any device Reset. The input
clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control
bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer 2 module has an 8-bit period
register, PR2. The value of Timer 2 increments from 00h until it matches PR2
and then resets to 00h on the next increment cycle. PR2 is a readable and
writable register. The PR2 register is initialized to FFh upon Reset. The match
output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16
scaling inclusive) to generate a TMR2 interrupt (latched in flag bit, TMR2IF
(PIR1<1>)). Timer 2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Register
memory organization of timer 2 module is given in the table below.
Register Memory
Organization in Timer 2
USART Modules in PIC 16F877
The Universal Synchronous
Asynchronous Receiver Transmitter (USART) module is one of the serial I/O
modules for communication interfacing functions with other devices/units. USART
is also known as a Serial Communications Interface or SCI. The USART can be
configured as a full-duplex asynchronous system that can communicate with
peripheral devices, such as CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that can communicate with
peripheral devices, such as Analog-to-Digital (A/D) or Digital-to-Analog (D/A)
integrated circuits, serial EPROM’s, and so on. Usually PIC 16F877 consists of
two USART modules (USART1, USART2). These ports can be configured in the
following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The USART module also has a
multi-processor communication capability using 9-bit address detection.
USART Baud Rate Generator (BRG)
The baud rate generator (BRG)
supports both the Asynchronous and Synchronous modes of the USART modules. It
is a dedicated 8-bit baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous mode, bit BRGH also
controls the baud rate.
Registers associated with baud rate
generator is shown below.
USART Baud Rate Generator (BRG) –
Registers
USART Asynchronous Mode
In asynchronous mode, the USART
uses standard Non-Return to- Zero (NRZ) format (one Start bit, eight or nine
data bits and one Stop bit). The most commonly used data format is 8 bits. An
on-chip, dedicated, 8-bit Baud Rate Generator can be used to derive standard
baud rate frequencies from the oscillator. The USART transmits and receives the
LSB (Least Significant Bit) first. The transmitter and receiver are
functionally independent but use the same data format and baud rate. The baud
rate generator produces a clock, either x16 or x64 of the bit shift rate,
depending on bit “BRGH “. Parity is not supported by the hardware but can be
implemented in software (and stored as the ninth data bit). Asynchronous mode
is stopped during Sleep. Asynchronous mode is selected by clearing bit SYNC.
The USART Asynchronous module
consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
USART Asynchronous Transmitter
USART transmitter (simply called
TX) is commonly used for data transmission process. The data transmission is
possible through various digital formats. The path of the transmission vary
according to the requirements (e.g.: infrared, Bluetooth, etc.). A simple block
diagram of a USART transmitter is shown below. . The heart of the USART
transmitter is the Transmit (Serial) Shift Register (TSR). The shift register
obtains its data from the Read/Write Transmit Buffer, TXREG. The TXREG register
is loaded with data in software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As soon as the Stop bit is
transmitted, the TSR is loaded with new data from the TXREG register (if
available). The simple block diagram of a USART transmitter is given below.
USART Transmitter Block Diagram
The registers associated with USART
asynchronous transmission is shown in the table below.
USART Asynchronous Transmission –
Registers
USART Asynchronous Receiver
The USART asynchronous receiver is
a data reception unit which is used for data reception from other communication
medias such as RF modules, Bluetooth, infrared modules (IR), etc. The simple
block diagram of a USART receiver is shown in the figure below. The data is
received on the RC7/RX/DT pin and drives the data recovery block. The data
recovery block is actually a high-speed shifter, operating at x16 times the
baud rate; whereas the main receive serial shifter operates at the bit rate or
at FOSC. Once Asynchronous mode is selected, reception is enabled by setting
bit CREN .The heart of the receiver is the Receive (Serial) Shift Register
(RSR). After sampling the Stop bit, the received data in the RSR is transferred
to the RCREG register (if it is empty). If the transfer is complete, flag bit,
RCIF (PIR1<5>), is set.
USART Receiver Block Diagram
The registers associated with the
USART receiver is given in the table below.
USART Asynchronous Reception –
Registers
Applications of USART Modules
1)
Used for Bluetooth communications.
2)
Widely used in Infrared (IR) communications.
3)
USART modules used with other RF communication purposes – AM, FM, QPSK, PSK,
FSK, Wi-Fi, and so on.
CAPTURE/COMPARE/PWM (CCP) Modules in PIC 16F877
Capture-Compare-Pulse-Width-Module (CCP) is a
special module designs for modulation and waveform generation applications.
This module basically works on three different modes (capture/compare and PWM
odes). The PIC 16F877 chip contains two CCP ports (CCP1 and CCP2). Each of this
CCP module contains 16 bit registers which works as
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle registers
The CCP1 and CCP2 modules are identical in its operation
except in its special event trigger operation. In each CCP modules, the
capture, compare and PWM modes using different timer resources. The table below
shows the different CCP modes and its timer resources. The detailed
explanations and functions of CCP module is given below.
CCP Timer Source-Interaction
CCP1 Module
Capture/Compare/PWM Register 1 (CCPR1) is a 16 bit
register comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high
byte). The CCP1CON register controls the operation of CCP1. The special event
trigger is generated by a compare match and will reset Timer1.
CCP2 Module
Capture/Compare/PWM Register 2 (CCPR2) is comprised
of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON
register controls the operation of CCP2. The special event trigger is generated
by a compare match and will reset Timer1 and start an A/D conversion (if the
A/D module is enabled).
Capture Mode
capture is made, the interrupt request flag In
Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when
an event occurs on pin RC2/CCP1.
An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits, CCP1M3:CCP1M0
(CCPxCON<3:0>). When a bit, CCP1IF (PIR1<2>), is set. The interrupt
flag must be cleared in software. If another capture occurs before the value in
register CCPR1 is read, the old captured value is overwritten by the new value.
The block diagram of capture mode is shown below.
Capture Mode
Block Diagram
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair value. When a match occurs,
the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of
control bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt
flag bit CCP1IF is set. The compare mode block diagram is shown below.
Compare Mode Block
Diagram
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since the CCP1 pin is
multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared
to make the CCP1 pin an output. Figure shows a simplified block diagram of the
CCP module in PWM mode.
PWM Mode Block Diagram
Setup for PWM Operation
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the CCPR1L
register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2 by
writing to T2CON.
5. Configure the CCP1 module for PWM operation.
The table below shows PWM FREQUENCIES and
RESOLUTIONS AT 20 MHz and registers associated with CCP timer1/2 modules.
Register
Organization-1
Register Organization-2
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